Posts by Collection

portfolio

Verilog Point of Sale Terminal on FPGA

Prototype POS terminal on a DE1-SoC (Cyclone V) FPGA with VGA display, barcode entry, cart management, and real-time price calculation — implemented in Verilog HDL.

Home Security System

AI-driven face recognition security system on Jetson Nano with real-time intrusion detection and Google Drive logging.

Milestone IP Integration

Modular Python library and PyQt5 GUI for real-time IP-based video streaming with Milestone’s VMS using custom SOAP/TCP messaging and multithreaded decoding.

ARM-Subset Multicycle CPU on FPGA

Progressive implementation of an ARM-like processor in Verilog — from a parametrized ALU to a full multicycle CPU with branching, synthesized on an Altera DE0-Nano (Cyclone IV).

Analog Sound Level Indicator Circuit

Custom analog sound-level indicator using electret microphone and multi-stage op-amp amplification to classify ambient noise into four thresholds, driving an LED via PWM.

publications

Paper Title Number 4

Published in GitHub Journal of Bugs, 2024

This paper is about fixing template issue #693.

Recommended citation: Your Name, You. (2024). "Paper Title Number 3." GitHub Journal of Bugs. 1(3).
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talks

teaching

Teaching experience 1

Undergraduate course, University 1, Department, 2014

This is a description of a teaching experience. You can use markdown like any other post.

Teaching experience 2

Workshop, University 1, Department, 2015

This is a description of a teaching experience. You can use markdown like any other post.