Verilog Point of Sale Terminal on FPGA
Overview
Design and implementation of a prototype POS machine on a Terasic DE1-SoC (Intel Cyclone V 5CSEMA5F31C6) using Verilog HDL. The system manages a 12-product database, supports three distinct operation modes controlled by slide switches, and drives a full-screen VGA interface with real-time visual feedback.
Operation Modes
- Barcode Mode: 4-digit barcode entry via push buttons (barcodes 1234–4133); matching products are highlighted dynamically before quantity entry.
- Browse Mode: 4-directional navigation through the product menu with combination-press select; selected item index shown on 7-segment display.
- Cart Mode: Review and remove cart items; running total updated in real time; red flash when cart is empty.
Key Features
- Product Database: 12 items with unique barcodes and prices ($0.50–$9.95); balance displayed in two-decimal fixed-point format.
- Visual Feedback: Color dimming for invalid actions (8-bit indexed color: 3R 3G 2B); dynamic cart capacity indicator.
- VGA Integration: 640×480 @60 Hz display using block ROM; custom image pipeline PNG→BMP→TXT→
.tvfor FPGA ROM loading. - Hardware Debouncing: Push buttons debounced at 4 Hz to eliminate contact bounce.
Technology Stack
- Hardware: Terasic DE1-SoC, Intel Cyclone V FPGA, VGA port, push buttons, DIP switches, 7-segment display
- Languages & Tools: Verilog HDL, SystemVerilog, Quartus Prime 20.1.1, MATLAB (image conversion)
- Key Modules:
VGA_SYNC.v,PushButton_Debouncer.v,which_digit.v,im_read.sv, 4× block RAM image modules - Clock Management: 25 MHz VGA clock derived from 50 MHz FPGA clock; 4 Hz debounced clock for button inputs.
Highlights
- Reduced compilation time from ~40 min to under 5 min by splitting the VGA background ROM across four submodules, moving storage from CLBs to dedicated block RAM.
- Implemented pixel-level VGA synchronization with correct front/back porch and sync pulse timing.
- Rendered 30×30 B/W digit bitmaps on-screen via
readmembfor real-time price and quantity display.